AT24C256B View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT24C256B' PDF : 24 Pages View PDF
AT24C256B
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9
cycles, (c) create another start bit followed by stop bit condition as shown below. The device is
ready for next communication after above steps have been completed.
Figure 4-3. Software Reset
Start bit
Dummy Clock Cycles
Start bit
Stop bit
SCL
1
2
3
8
9
SDA
Figure 4-4. Bus Timing
SCL
SDA IN
tSU.STA
SDA OUT
tF
tLOW
tHD.STA
tHIGH
tHD.DAT
tLOW
tSU.DAT
tAA
tDH
Figure 4-5. Write Cycle Timing
SCL
tR
tSU.STO
tBUF
SDA
8th BIT
ACK
WORDn
STOP
CONDITION
(1)
twr
START
CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
7
5279C–SEEPR–3/09
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