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AT24CS256W-10SC-2.7 View Datasheet(PDF) - Atmel Corporation

Part Name
Description
MFG CO.
AT24CS256W-10SC-2.7
Atmel
Atmel Corporation Atmel
'AT24CS256W-10SC-2.7' PDF : 12 Pages View PDF
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AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt
2.7-volt
5.0-volt
Symbol
Parameter
Min
Max
Min
Max
Min
Max Units
fSCL
tLOW
tHIGH
tAA
tBUF
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start(1)
400
1000
1000 kHz
1.3
0.6
0.6
µs
1.0
0.4
0.4
µs
0.1
0.9
0.05 0.55 0.05 0.55
µs
1.2
0.5
0.5
µs
tHD.STA
Start Hold Time
0.6
0.25
0.25
µs
tSU.STA
Start Set-up Time
0.6
0.25
0.25
µs
tHD.DAT
Data In Hold Time
0
0
0
µs
tSU.DAT
tR
tF
Data In Set-up Time
Inputs Rise Time(1)
Inputs Fall Time(1)
100
100
100
ns
0.3
0.3
0.3
µs
300
100
100
ns
tSU.STO
Stop Set-up Time
0.6
0.25
0.25
µs
tDH
Data Out Hold Time
50
50
50
ns
tWR
Write Cycle Time
20
10
10
ms
Endurance(1)
5.0V, 25°C, Page Mode
100K
100K
100K
Write
Cycles
Notes: 1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
RL (connects to VCC): 1.3K(2.7V, 5V), 10K(1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: 50ns
Input and output timing reference voltages: 0.5VCC
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24CS128/256 features a low
power standby mode which is enabled: a) upon power-up
and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
4
AT24CS128/256
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