AT24RF08C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT24RF08C' PDF : 21 Pages View PDF
AT24RF08C
State Transition Diagram
Global Reset Quiet
Ack
in
Window
INIT
No Mod
Global Reset Quiet / Set Quiet
Mod Outside Ack Window
UNSELECTED
Global Write Word
Global Set Tamper
Other modulation ignored
Invalid
Command/Data
Wait for
no mod.
Global
Reset
Quiet
Global Reset Quiet
Read
Page/Word
SELECTED
3 bit listen
Set Quiet
Write
Page/Word
Write Done
Set BL / PL
Set Tamper
All Globals
Read Page/Word
Invalid
Command/Data
QUIET
Global Write Word
Global Set Tamper
Other modulation ignored
Set Quiet
Write in
Progress
Write Page/Word
SELECTED
Long
Listen
Set BL / PL
Set Tamper
All Globals
Commands listed in italics
Error Detection
In order to increase the reliability of data transmissions to
the AT24RF08C, an error detection field must be sent by
the reader after the command word and each byte of data
sent from the reader. This field is computed as the number
of bits turned on in the byte modulo 4. In order to prevent
the checksum from matching the data for repeated 0’s or
1’s, the least significant bit (c0) is then inverted. For the
command word, only the 6 varying bits (b7 - b2) are used to
compute the checksum.
There are several levels of error detection utilized to
prevent improper execution of a command. If the command
encoding is illegal, or the checksum is wrong, or if there is a
Manchester error in either the command or data or if there
is a protection failure, then the entire command will be
aborted. Once in that state, the device will wait a random
period of time before transmitting the header sequence.
On both ID and data sent from the chip, the chip generates
and transmits a single parity bit after each 8 data bits are
sent to the reader. Internally, parity is computed in such a
way that the number of 1s in each 9 bit group is even. The
start and stop bits are not included in the parity generation.
No parity is generated on the 4-bit header. It is expected
that the reader may either embed additional error detection
bits within the data and/or read the data two or more times
to reduce the rate of bit errors.
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