AT25P1024C1-10CI-2.7_06 View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'AT25P1024C1-10CI-2.7_06' PDF : 17 Pages View PDF
Table 7. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write cycle
is in progress.
Bit 1 (WEN)
Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1” indicates the device
is write enabled.
Bit 2 (BP0)
See Table 8.
Bit 3 (BP1)
See Table 8.
Bits 4-6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 9.
Bits 0-7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25P1024 is divided into four array segments. Top
quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the
data within any selected segment will therefore be read only. The block write protection
levels and corresponding status register control bits are shown in Table 8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25P1024
0
0
0
1(1/4)
0
1
None
01800 - 01FFFF
2(1/2)
1
0
010000 - 01FFFF
3(All)
1
1
0000 - 01FFFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0”. When the device is hard-
ware write protected, writes to the Status Register, including the block protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
0
0
1
WP
WEN
X
0
X
1
Low
0
Protected
Blocks
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Status Register
Protected
Writable
Protected
8 AT25P1024
1082I–SEEPR–7/06
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