AT45D32SSUB1D-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45D32SSUB1D-CU' PDF : 57 Pages View PDF
AT45DB321D
21.6 Reset Timing
CS
SCK
RESET
SO (OUTPUT)
HIGH IMPEDANCE
tREC
tRST
tCSS
HIGH IMPEDANCE
SI (INPUT)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
21.7 Command Sequence for Read/Write Operations for Page Size 512 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
SI (INPUT)
CMD 8 bits 8 bits 8 bits
MSB
XX XXXXX XXXXXXXXX XXXX XXXX
LSB
Don’t Care
Bits
Page Address
(A21 - A9)
Byte/Buffer Address
(A8 - A0/BFA8 - BFA0)
21.8 Command Sequence for Read/Write Operations for Page Size 528 Bytes (Except Status
Register Read, Manufacturer and Device ID Read)
SI (INPUT)
CMD 8 bits 8 bits 8 bits
MSB
X X X XX X X X X X X X X X X X X X X X X X X X
LSB
1 Don’t Care Page Address
Bit
(PA12 - PA0)
Byte/Buffer Address
(BA9 - BA0/BFA9 - BFA0)
39
3597N–DFLASH–04/09
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