Reset Timing (Inactive Clock Polarity Low Shown)
CS
SCK
RESET
SO
HIGH IMPEDANCE
SI
tREC
tRST
tCSS
HIGH IMPEDANCE
Command Sequence for Read/Write Operations (Except Status Register Read)
SI
CMD 8 bits 8 bits 8 bits
MSB
r r r r XXXX XXXX XXXX XXXX XXXX
LSB
Reserved for
larger densities
Page Address
(PA10-PA0)
Byte/Buffer Address
(BA8-BA0/BFA8-BFA0)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 4M bit or smaller.
3. For densities larger than 4M bit, the “r” bits become the most significant Page Address bit for the appropriate density.
8
AT45DB041