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AT45DB041B View Datasheet(PDF) - Atmel Corporation

Part Name
Description
MFG CO.
'AT45DB041B' PDF : 33 Pages View PDF
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3. Block Diagram
AT45DB041B
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB041B is divided into three levels of
granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis; however, the optional
erase operations can be performed at the block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 8 Pages
2112 bytes (2K + 64)
SECTOR 1 = 248 Pages
65,472 bytes (62K + 1984)
SECTOR 0
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
SECTOR 2 = 256 Pages
67,584 bytes (64K + 2K)
SECTOR 3 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
8 Pages
SECTOR 4 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 5 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 254
BLOCK 255
Block = 2112 bytes
(2K + 64)
PAGE 2045
PAGE 2046
PAGE 2047
Page = 264 bytes
(256 + 8)
3
3443C–DFLSH–5/05
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