AT45DB081D-MU-2.5 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB081D-MU-2.5' PDF : 53 Pages View PDF
Atmel AT45DB081D
16. Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device
will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a
high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode
3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive
clock state.
16.1
Initial Power-up/Reset Timing Restrictions
At power up, the device must not be selected until the supply voltage reaches the VCC (min.) and
further delay of tVCSL. During power-up, the internal Power-on Reset circuitry keeps the device in
reset mode until the VCC rises above the Power-on Reset threshold value (VPOR). At this time, all
operations are disabled and the device does not respond to any commands. After power up is
applied and the VCC is at the minimum operating voltage VCC (min.), the tVCSL delay is required
before the device can be selected in order to perform a read operation.
Similarly, the tPUW delay is required after the VCC rises above the Power-on Reset threshold
value (VPOR) before the device can perform a write (Program or Erase) operation. After initial
power-up, the device will default in Standby mode.
Table 16-1. Initial Power-up/Reset Timing Restrictions
Symbol Parameter
Min
Typ
Max
Units
tVCSL
tPUW
VPOR
VCC (min.) to Chip Select low
70
Power-Up Device Delay before Write Allowed
Power-ON Reset Voltage
1.5
µs
20
ms
2.5
V
17. System Considerations
The Atmel® RapidS™ serial interface is controlled by the clock SCK, serial input SI and chip
select CS pins. These signals must rise and fall monotonically and be free from noise. Excessive
noise or ringing on these pins can be misinterpreted as multiple edges and cause improper
operation of the device. The PC board traces must be kept to a minimum distance or appropri-
ately terminated to ensure proper operation. If necessary, decoupling capacitors can be added
on these pins to provide filtering against noise glitches.
As system complexity continues to increase, voltage regulation is becoming more important. A
key element of any voltage regulation scheme is its current sourcing capability. Like all Flash
memories, the peak current for Atmel DataFlash® occur during the programming and erase
operation. The regulator needs to supply this peak current requirement. An under specified reg-
ulator can cause current starvation. Besides increasing system noise, current starvation during
programming or erase can lead to improper operation and possible data corruption.
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3596M–DFLASH–5/10
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