AT45DB081D-SSU-2.5 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB081D-SSU-2.5' PDF : 54 Pages View PDF
21.6 Reset Timing
CS
SCK
RESET
SO (OUTPUT)
HIGH IMPEDANCE
tREC
tRST
tCSS
HIGH IMPEDANCE
SI (INPUT)
Note: The CS signal should be in the high state before the RESET signal is deasserted
21.7 Command Sequence for Read/Write Operations for Page Size 256-Bytes
(Except Status Register Read, Manufacturer and Device ID Read)
SI (INPUT)
CMD 8 bits 8 bits 8 bits
MSB
XXXX XXXX XXXXX XX XXXX XXXX
LSB
4 Don’t Care
Bits
Page Address
(A19 - A8)
Byte/Buffer Address
(A7 - A0/BFA7 - BFA0)
21.8 Command Sequence for Read/Write Operations for Page Size 264-Bytes
(Except Status Register Read, Manufacturer and Device ID Read)
SI (INPUT)
CMD 8 bits 8 bits 8 bits
MSB
XXX XX XXXX XXXX XX X XXXX XXXX
LSB
3 Don’t Care Page Address
Bits
(PA11 - PA0)
Byte/Buffer Address
(BA8 - BA0/BFA8 - BFA0)
38 Atmel AT45DB081D
3596M–DFLASH–5/10
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