AT45DB321B-CI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB321B-CI' PDF : 32 Pages View PDF
AT45DB321B
Reset Timing (Inactive Clock Polarity Low Shown)
CS
SCK
RESET
SO
HIGH IMPEDANCE
tREC
tRST
tCSS
HIGH IMPEDANCE
SI
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
SI
CMD 8 bits 8 bits 8 bits
MSB
r X X X XXXX XXXX XXXX XXXX XXXX
LSB
Reserved for Page Address
larger densities (PA12-PA0)
Byte/Buffer Address
(BA9-BA0/BFA9-BFA0)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 32M bits or smaller.
3. For densities larger than 32M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
15
2223E–DFLASH–11//03
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