AT45DB321B-CI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB321B-CI' PDF : 32 Pages View PDF
Input Test Waveforms and Measurement Levels
AC
2.4V
DRIVING
LEVELS 0.45V
tR, tF < 3 ns (10% to 90%)
2.0 AC
MEASUREMENT
0.8 LEVEL
Output Test Load
DEVICE
UNDER
TEST
30 pF
AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal
being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK sig-
nal being high when CS makes a high-to-low transition. Both waveforms show valid
timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-
high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2
shows timing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
CS
SCK
tCSS
tWH
tWL
tCSH
tV
HIGH IMPEDANCE
SO
tHO
VALID OUT
tSU
tH
SI
VALID IN
tCS
tDIS
HIGH IMPEDANCE
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
CS
SCK
SO
SI
tCSS
tWL
tWH
tV
HIGH Z
tSU
tHO
VALID OUT
tH
VALID IN
tCSH
14 AT45DB321B
tCS
tDIS
HIGH IMPEDANCE
2223E–DFLASH–11//03
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