AT45DB321C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT45DB321C' PDF : 40 Pages View PDF
3. Block Diagram
AT45DB321C
WP
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 1 (528 BYTES)
BUFFER 2 (528 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB321C is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram†illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page by page basis. The erase operations can
be performed at the block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
4224 bytes (4K + 128)
SECTOR 0b = 504 Pages
266,112 bytes (252K + 8064)
SECTOR 0a
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
SECTOR 1 = 512 Pages
270,336 bytes (256K + 8K)
SECTOR 2 = 512 Pages
270,336 bytes (256K + 8K)
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
SECTOR 14 = 512 Pages
270,336 bytes (256K + 8K)
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
8 Pages
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 15 = 512 Pages
270,336 bytes (256K + 8K)
BLOCK 1022
BLOCK 1023
Block = 4224 bytes
(4K + 128)
PAGE 8189
PAGE 8190
PAGE 8191
Page = 528 bytes
(512 + 16)
3
3387M–DFLASH–2/08
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