AT45DB321E-MWUF2B-T View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
AT45DB321E-MWUF2B-T
Unspecified
'AT45DB321E-MWUF2B-T' PDF : 72 Pages View PDF
22.
AC Waveforms
Four different timing waveforms are shown in Figure 22-1 through Figure 22-4. Waveform 1 shows the SCK signal being
low when CS makes a high-to-low transition and Waveform 2 shows the SCK signal being high when CS makes a
high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified
as tWL). Timing Waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 85MHz. Waveforms 1
and 2 are compatible with SPI Mode 0 and SPI Mode 3, respectively.
Waveform 3 and 4 illustrate general timing diagram for RapidS serial interface. These are similar to Waveform 1 and 2,
except that output SO is not restricted to become valid during the tWL period. These timing waveforms are valid over the
full frequency range (maximum frequency = 85MHz) of the RapidS serial case.
Figure 22-1. Waveform 1 = SPI Mode 0 Compatible
CS
SCK
SO
SI
tCSS
tWH
tWL
tCSH
tV
High-impedance
tSU
tH
Valid In
tHO
Valid Out
tCS
tDIS
High-impedance
Figure 22-2. Waveform 2 = SPI Mode 3 Compatible
CS
SCK
SO
SI
tCSS
tWL
tWH
tV
High Z
tSU
tHO
Valid Out
tH
Valid In
tCSH
tCS
tDIS
High-impedance
AT45DB321E 52
8784E–DFLASH–10/2013
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