Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 5.0V ± 20% and Load Capacitance = 80 pF.
Symbol
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Parameter
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
12 MHz Osc
Min
Max
1.0
700
50
0
700
Variable Oscillator
Min
Max
Units
12tCLCL
µs
10tCLCL - 133
ns
2tCLCL - 33
ns
0
ns
10tCLCL - 133 ns
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms(1) Float Waveforms (1)
Note:
1. AC Inputs during testing are driven at VCC - 0.5V
for a logic 1 and 0.45V for a logic 0. Timing meas-
urements are made at VIH min. for a logic 1 and
VIL max. for a logic 0.
Note:
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when a 100 mV change from
the loaded VOH/VOL level occurs.
1-16
AT48801