AT48802-16QC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT48802-16QC' PDF : 23 Pages View PDF
AT48802
Audio and Line Controls (Continued)
TX CHOP
Transmit Chop is timed with TDD and can turn off the
audio used to modulate transmit RF during the receive pe-
riod. If the RF module has a single synthesizer then this
function is needed to prevent a large sidetone due to re-
ceive RF local oscillator modulation. R13 b0-1 control this
function to be high, low, TDD or inverse TDD.
AUD T/H and AUX T/H
Both Audio Track/Hold and Auxiliary Track/Hold have the
same, independently settable function. If this chip is used
in a high rate TDD system with analog audio modulation
then it is necessary to track and hold the receive audio
since it is only present half the time at the TDD rate of 7.5
kHz. AUD T/H provides a fully adjustable TDD rate pulse
to do this. The pulse width and pulse timing are fully ad-
justable over the range of 1 TDD cycle in increments of
1/64 of a TDD cycle, i.e., 2.1us steps, for a 15.36 MHz
clock. The delay and pulse width are programmable via
RE b0-5 and RF b0-5 (R10 b0-5 and RF b0-5 for AUX
T/H). These register settings provide TDD/2 adjustability,
and rest of the range is provided by RE b6-7 (or R10 b6-7
for AUX T/H) which can invert the output, or cause it to be
always high or always low.
Ringer and ATTN DP
Ringer is controlled by R4 b5-6 and can be output always
high, always low, three-state and 1875 Hz tone to drive a
speaker or piezo transducer. Attenuator Dial Pulse is
available to drive a relay when needed for pulse dialing. In
the handset of a telephone there is no relay (it is in the
base) so this output could be used to turn on/off an audio
attenuator.
Microprocessor Bi-Directional Bus
Interface
Most control functions, including most Spread-Spectrum
controls, PN registers, RF Controls, and telephone con-
trols are loadable into a set of control registers via an 8 bit
data bus. This 8 bit bi-directional address / data bus, AD7
- AD0 (LSB), is compatible with the 80C51 / 80C52 family
of microcontroller. Register data can be read back via the
same data bus. Twenty-one control registers (HEX 00 to
HEX 14) are provided for complete implementation of
cordless phone or wireless communication systems. Reg-
ister 8 and Register 14 are read only. Do not write to R14
b7.
The microcontroller may run using the same 15.36 MHz
master clock that the ASIC uses. However that is not ab-
solutely necessary. In any case, it must be rated to oper-
ate to at least 16 MHz frequency.
Data Bus Write Cycle Timing
The bus multiplexes address information as well as data.
Address decoding is internally provided. The register ad-
dress is directly mapped to the low-order address bits.
That is, register 0 has the address code of HEX 00, while
register A has the address code of HEX 0A. During a
WRITE cycle, the address is latched into the address de-
coder by the falling edge of the ALE signal. Data from the
microprocessor must be valid when the WR signal goes
from a low-to-high state. Figure 4 shows the WRITE cycle
timing.
Figure 4. Write Cycle Timing Diagram
2-9
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