AT52BC3221AT View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT52BC3221AT' PDF : 36 Pages View PDF
Write Cycle (1)
(PWE Controlled, ZZ = VIH)
Address
PCS1
PUB, PLB
PWE
Data In
Data Out
Write Cycle (2)
(PCS1 Controlled, ZZ = VIH)
Address
PCS1
PUB, PLB
PWE
Dat a In
Data Out
Write Cycle (3)
(PUB, PLB Controlled, ZZ = VIH)
AT52BC3221A(T)
S
High-Z
Data Undefined
C
W (2)
W
W
P(1)
HZ
R(4)
W
Data Valid
W
High-Z
S
High-Z
C
W (2)
W
W
P(1)
W
Data Valid
R(4)
High-Z
Address
PCS1
PUB, PLB
S
PWE
Data In
C
W(2)
W
W
P (1)
R (4)
W
Data Valid
Notes:
Data Out
High-Z
High-Z
1. A write occurs during the overlap (tWP) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with
asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write
ends at the earliest transition when PCS1 goes high and PWE goes high. The tWP is measured from the beginning of write to
the end of write.
2. tCW is measured from the PCS1 going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as PCS1 or PWE going high.
5. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 40 µs.
31
3466A–STKD–11/04
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