AT52BC3221AT View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT52BC3221AT' PDF : 36 Pages View PDF
AT52BC3221A(T)
Figure 1. Data Polling Algorithm
(Configuration Register = 00)
START
Read I/O7 - I/O0
Addr = VA
YES
I/O7 = Data?
NO
NO
I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Addr = VA
I/O7 = Data?
YES
NO
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful,
Device in
Read Mode
Notes:
1. VA = Valid address for programming. During a sec-
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
2. I/O7 should be rechecked even if I/O5 = “1”
because I/O7 may change simultaneously with
I/O5.
Figure 2. Data Polling Algorithm
(Configuration Register = 01)
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Toggle Bit =
NO
Toggle?
YES
NO I/O3, I/O5 = 1?
YES
Read I/O7 - I/O0
Twice
Toggle Bit =
NO
Toggle?
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Exit Command
Program/Erase
Operation
Successful
Note:
1. VA = Valid address for programming. During a sec-
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
9
3466A–STKD–11/04
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