AT52BR1672-85CI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT52BR1672-85CI' PDF : 39 Pages View PDF
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
tCW
SCS1
tWR(2)
SCS2
SUB, SLB
SWE
DATA IN
DATA OUT
tAS
HIGH-Z tAS
tAW
tBW
tWP
tWHZ(3)(7)
tDW
DATA VALID
tDH
tOW
(5) (5)
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
ADDRESS
tAS
SCS1
SCS2
tWC
tCW
tAW
tBW
SUB, SLB
tWP
SWE
DATA IN
HIGH-Z
tWR(2)
tDW
tDH
DATA VALID
DATA OUT
HIGH-Z
Notes:
1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
28 AT52BR1672(T)/1674(T)
2604B–STKD–09/02
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