AT80C51RA2-3CSCV View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT80C51RA2-3CSCV' PDF : 86 Pages View PDF
Bit Number
7
Bit
Mnemonic
FE
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
Serial port Mode bit 1
SM0 SM1ModeDescriptionBaud Rate
6
SM1
0 0 0Shift RegisterFXTAL/12 (/6 in X2 mode)
0 1 18-bit UARTVariable
1 0 29-bit UARTFXTAL/64 or FXTAL/32 (/32, /16 in X2 mode)
1 1 39-bit UARTVariable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
5
SM2
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually
mode 1. This bit should be cleared in mode 0.
Reception Enable bit
4
REN
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
3
TB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
2
RB8
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag
1
TI
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop
bit in the other modes.
Receive Interrupt flag
0
RI
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 6-11. and Figure 6-
12. in the other modes.
Reset Value = 0000 0000b
Bit addressable
Table 6-15. PCON Register
PCON - Power Control Register (87h)
7
6
5
SMOD1
SMOD0
-
4
3
2
1
0
POF
GF1
GF0
PD
IDL
38 AT/TS8xC51Rx2
4188F–8051–01/08
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