AT80C51RA2-3CSCV View Datasheet(PDF) - International Rectifier
Part Name
Description
MFG CO.
'AT80C51RA2-3CSCV' PDF : 85 Pages View PDF
AT/TS8xC51Rx2
5.4 Dual Data Pointer Register
The additional data pointer can be used to speed up code execution and reduce code size in a
number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 (Table 5-3) that allows the program code to switch between
them (Refer to Figure 5-3).
Figure 5-3. Use of Dual Pointer
External Data Memory
7
0
DPS
AUXR1(A2H)
DPTR1
DPTR0
DPH(83H) DPL(82H)
Table 5-3. AUXR1: Auxiliary Register 1
AUXR1
Address 0A2H
-
-
-
-
GF3
-
-
DPS
Reset value
X
X
X
X
0
X
X
0
Symbol
-
Function
Not implemented, reserved for future use (1)
DPS
Data Pointer Selection.
DPS
Operating Mode
0
DPTR0 Selected
1
DPTR1 Selected
GF3
This bit is a general purpose user flag(2).
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new feature. In that case, the reset value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
GF3 will not be available on first version of the RC devices.
15
4188E–8051–08/06
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