• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 6-7 shows the CCAPMn settings for the various PCA functions.
.
Table 6-6.
CCAPMn: PCA Modules Compare/Capture Control Registers
CCAPMn Address
n=0-4
CCAPM0=0DAH
CCAPM1=0DBH
CCAPM2=0DCH
CCAPM3=0DDH
CCAPM4=0DEH
Reset value
- ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn
X
0
0
0
0
0
0
0
Symbol
-
ECOMn
CAPPn
CAPNn
MATn
TOGn
PWMn
ECCFn
Function
Not implemented, reserved for future use. (1)
Enable Comparator. ECOMn = 1 enables the comparator function.
Capture Positive, CAPPn = 1 enables positive edge capture.
Capture Negative, CAPNn = 1 enables negative edge capture.
Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register
causes the CCFn bit in CCON to be set, flagging an interrupt.
Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register
causes the CEXn pin to toggle.
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an
interrupt.
1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0,
and its active value will be 1. The value read from a reserved bit is indeterminate.
Table 6-7. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn CAPNn
0
0
0
MATn
0
X
1
0
0
X
0
1
0
X
1
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
TOGn
0
0
0
0
0
1
0
X
PWMm ECCFn Module Function
0
0
No Operation
0
X
16-bit capture by a positive-edge trigger
on CEXn
0
X
16-bit capture by a negative trigger on
CEXn
0
X
16-bit capture by a transition on CEXn
0
X
16-bit Software Timer / Compare mode.
0
X
16-bit High Speed Output
1
0
8-bit PWM
0
X
Watchdog Timer (module 4 only)
28 AT/TS8xC51Rx2
4188E–8051–08/06