AT80C51RA2-3CSUL View Datasheet(PDF) - International Rectifier
Part Name
Description
MFG CO.
'AT80C51RA2-3CSUL' PDF : 85 Pages View PDF
11.5.15
Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by
two.
Figure 11-14. Clock Waveforms
INTERNAL
CLOCK
STATE4
P1P2
STATE5 STATE6
P1P2
P1P2
STATE1
P1P2
STATE2 STATE3
P1P2
P1P2
STATE4 STATE5
P1P2
P1P2
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
P0
DATA
SAMPLED
FLOAT
P2 (EXT)
READ CYCLE
RD
P0
P2
WRITE CYCLE
WR
P0
P2
PCL OUT
DATA
SAMPLED
FLOAT
PCL OUT
INDICATES ADDRESS TRANSITIONS
DATA
SAMPLED
FLOAT
PCL OUT
DPL OR Rt OUT
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
DPL OR Rt OUT
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PORT OPERATION
MOV DEST P0
OLD DATA NEW DATA
P0 PINS SAMPLED
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
P1, P2, P3 PINS SAMPLED
SERIAL PORT SHIFT CLOCK RXD SAMPLED
TXD (MODE 0)
P0 PINS SAMPLED
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to prop-
agate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on
variables such as temperature and pin loading. Propagation also varies from output to output
and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are
approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated
in the AC specifications.
72 AT/TS8xC51Rx2
4188E–8051–08/06
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