Figure 3.
SCL
Bus Timing for 2 wire communications: SCL: Serial Clock, SDA – Serial Data I/O
tF
tLOW
tHIGH
tLOW
SDA IN
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tAA
tDH
SDA OUT
tR
tSU.STO
tBUF
Figure 4. Write Cycle Timing: SCL: Serial Clock, SDA – Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
STOP
CONDITION
(1)
twr
START
CONDITION
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.
6 AT88SC0104C
2021KS–SMEM–10/09