Figure 2. Bus Timing for 2 wire communications
SCL: Serial Clock, SDA: Serial Data I/O
AT88SC0104C
Figure 3. Write Cycle Timing:
SCL: Serial Clock, SDA: Serial Data I/O
SCL
SDA
8th BIT
ACK
WORDn
Note:
STOP
CONDITION
twr(1)
START
CONDITION
The write cycle time twr is the time from a valid stop condition of a write sequence to the
end of the internal clear/write cycle.
Figure 4. Data Validity
5
2021GS–SMEM–7/06