AT88SC0104CA View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

AT88SC0104CA

CryptoMemory

Atmel Corporation 

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4. Connection Diagram

Figure 3. Connection Diagram

2.7v - 5.5v

Microprocessor

2.7v - 3.6v

CryptoMemory

SDA

SCL

5. Pin Descriptions

5.1. Supply Voltage (VCC)

The VCC input is a 2.7V to 3.6V positive voltage supplied by the host.

5.2.

Clock (SCL/CLK)

When using the asynchronous T = 0 protocol, the CLK (SCL) input provides the device with a carrier frequency f. The

nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/ f.

When using the synchronous protocol, data clocking is done on the positive edge of the clock when writing to the

device and on the negative edge of the clock when reading from the device.

5.3.

Reset (RST)

The AT88SC0104CA provides an ISO 7816-3 compliant asynchronous Answer-To-Reset (ATR) sequence. Upon

activation of the reset sequence, the device outputs bytes contained in the 64-bit Answer-To-Reset register. An internal

pull-up on the RST input pad allows the device to operate in synchronous mode without bonding RST. The

AT88SC0104CA does not support an Answer-To-Reset sequence in the synchronous mode of operation.

5.4.

Serial Data (SDA/IO)

The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number

of other open-drain or open-collector devices. An external pull-up resistor should be connected between SDA/IO and

VCC. The value of this resistor and the system capacitance loading the SDA/IO bus will determine the rise time of

SDA/IO. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will

allow higher frequency operations while drawing higher average power supply current. SDA/IO information applies to

both asynchronous and synchronous protocols.

4 AT88SC0104CA

5200ES–CRYPT–08/09

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