AT88SC1003-10WI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT88SC1003-10WI' PDF : 30 Pages View PDF
Figure 7. Compare
Address
An-1
An
An+1
CLK
tSC
tHC
tSC
I/O
Input
Note:
Input data is latched on the falling edge of CLK.
Comparison occurs on the next falling edge of CLK.
The address counter is incremented on the falling edge of CLK.
Figure 8. INC/CMP (before code presentation)
Address
An-1
An
An+1
CLK
I/O Output
Hi-Z
tSC
Input
tHC
tSC
Note:
After the rising edge of CLK on the address immediately preceding the security code or
erase keys, the I/O will be disabled (Hi-Z). This allows the input data to be set up before
comparing the first bit of each code.
22 AT88SC1003
2035B–SMEM–08/03
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