AT88SC1608 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT88SC1608' PDF : 25 Pages View PDF
Answer-to-reset
If RST is high during SCL clock pulse, the reset operation occurs according to the ISO
7816-10 synchronous answer-to-reset. The four bytes of the answer-to-reset register
are transmitted least significant bit (LSB) first on the 32 clock pulses provided on SCL.
Following a RST assertion, all password and authentication access privileges are reset.
The values programmed by Atmel are shown in Figure 9 below.
Figure 9. Answer-to-reset
R
E
S
E
T
$2C
$AA
$55
$A0
0011010001010101 10101010 00000101
D0
–
D7 D8
–
D15 D16
–
D23 D24
–
D31
Verify Password
Figure 10. Verify Password
S
T
A
R
T Command
Index
10110100
* * * * r p2 p1 p0 D7
A
A
C
C
K
K
Pw(0)
–
D0
D15
A
C
K
Pw(1)
–
D8
D23
A
C
K
Pw(2)
–
S
T
O
P
D16
A
C
K
1. Pw: Password, 3 bytes
2. The four bits “rppp” indicate the password to compare:
r = 0: Write password
r = 1: Read password
ppp: Password set number
(rppp = 0111 for the secure code)
Once the sequence is completed and a stop condition is issued, there is a nonvolatile
write cycle to update the associated attempts counter. In order to know whether or not
the inserted password was correct, the device requires the host to perform an ACK poll-
ing sequence with the specific device address of $B5. When the write cycle has been
completed, the ACK polling command ($B5, Read Configuration Zone) will return a valid
ACK. This command should be followed by the byte address of the respective PAC. If
the password presented is valid, the PAC will be set to $FF. If the password was not
valid, the PAC will have one additional bit written to “0”.
12 AT88SC1608
0971G–SMEM–04/04
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