AT89C51-20QC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT89C51-20QC' PDF : 15 Pages View PDF
AT89C51
Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)
Symbol
Parameter
12 MHz Osc
Variable Oscillator
Min Max
Min
Max
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
1.0
12tCLCL
700
10tCLCL-133
50
2tCLCL-117
0
0
700
10tCLCL-133
Units
µs
ns
ns
ns
ns
Shift Register Mode Timing Waveforms
INSTRUCTION
ALE
CLOCK
WRITE TO SBUF
OUTPUT DATA
CLEAR RI
INPUT DATA
0
1
2
3
4
5
6
7
8
tQVXH
0
tXHDV
VALID
tXLXL
tXHQX
1
VALID
2
tXHDX
VALID
3
VALID
4
VALID
5
VALID
6
7
SET TI
VALID
VALID
SET RI
AC Testing Input/Output Waveforms(1) Float Waveforms(1)
VCC - 0.5V
0.45V
0.2 VCC + 0.9V
TEST POINTS
0.2 VCC - 0.1V
VLOAD
V
+
LOAD
0.1V
V LOAD - 0.1V
Timing Reference
Points
V OL - 0.1V
V OL + 0.1V
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for Note:
a logic 1 and 0.45V for a logic 0. Timing measure-
ments are made at VIH min. for a logic 1 and VIL
max. for a logic 0.
1. For timing purposes, a port pin is no longer floating
when a 100 mV change from load voltage occurs. A
port pin begins to float when 100 mV change from
the loaded VOH/VOL level occurs.
4-41
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