19. Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down
is the last instruction executed. The on-chip RAM and Special Function Registers retain their
values until the Power-down mode is terminated. Exit from Power-down can be initiated either
by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not
change the on-chip RAM. The reset should not be activated before VCC is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and
stabilize.
Figure 19-1. Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 19-2. External Clock Drive Configuration
NC
XTAL2
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1
GND
Table 19-1. Status of External Pins During Idle and Power-down Modes
Mode
Program
Memory
ALE PSEN PORT0 PORT1 PORT2
Idle
Internal
1
1
Data
Data
Data
Idle
External
1
1
Float
Data Address
Power-down Internal
0
0
Data
Data
Data
Power-down External
0
0
Float
Data
Data
PORT3
Data
Data
Data
Data
20 AT89C51RC
1920C–MICRO–03/05