AT89LS8252-12PI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT89LS8252-12PI' PDF : 35 Pages View PDF
Serial Programming Algorithm
To program and verify the AT89LS8252 in the serial pro-
gramming mode, the following sequence is recommended:
1. Power-up sequence:
Apply power between VCC and GND pins.
Set RST pin to “H”.
If a crystal is not connected across pins XTAL1 and
XTAL2, apply a 3 MHz to 12 MHz clock to XTAL1 pin
and wait for at least 10 milliseconds.
2. Enable serial programming by sending the Pro-
gramming Enable serial instruction to pin MOSI/
P1.5. The frequency of the shift clock supplied at
pin SCK/P1.7 needs to be less than the CPU clock
at XTAL1 divided by 40.
3. The Code or Data array is programmed one byte at
a time by supplying the address and data together
with the appropriate Write instruction. The selected
memory location is first automatically erased before
new data is written. The write cycle is self-timed and
typically takes less than 2.5 ms at 5V and less than
10 ms at 2.7V.
4. Any memory location can be verified by using the
Read instruction which returns the content at the
selected address at serial output MISO/P1.6.
5. At the end of a programming session, RST can be
set low to commence normal operation.
Power-off sequence (if needed):
Set XTAL1 to “L” (if a crystal is not used).
Set RST to “L”.
Turn VCC power off.
Serial Programming Instruction
The Instruction Set for Serial Programming follows a 3-byte
protocol and is shown in the following table:
Instruction Set
Instruction
Programming Enable
Chip Erase
Read Code Memory
Write Code Memory
Read Data Memory
Write Data Memory
Write Lock Bits
Input Format
Byte 1
Byte 2
Byte 3
1010 1100 0101 0011 xxxx xxxx
1010 1100 xxxx x100 xxxx xxxx
aaaa a001 low addr xxxx xxxx
aaaa a010 low addr data in
00aa a101 low addr xxxx xxxx
00aa a110
1010 1100
low addr data in
x x111 xxxx xxxx
Operation
Enable serial programming interface after RST goes
high.
Chip erase both 8K & 2K memory arrays.
Read data from Code memory array at the selected
address. The 5 MSBs of the first byte are the high order
address bits. The low order address bits are in the
second byte. Data are available at pin MISO during the
third byte.
Write data to Code memory location at selected
address. The address bits are the 5 MSBs of the first
byte together with the second byte.
Read data from Data memory array at selected
address. Data are available at pin MISO during the third
byte.
Write data to Data memory location at selected address.
Write lock bits.
Set LB1, LB2 or LB3 = “0” to program lock bits.
Notes:
1. DATA polling is used to indicate the end of a write cycle which typically takes less than 10 ms at 2.7V.
2. “aaaaa” = high order address.
3. “x” = don’t care.
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AT89LS8252
0850C–MICRO–3/06
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