AT89S4D12-12JC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT89S4D12-12JC' PDF : 13 Pages View PDF
AT89S4D12
Oscillator Characteristics
An on-chip oscillator is provided with a minimum frequency
of 12 MHz and maximum frequency of 15 MHz over the
recommended operating conditions.
Each CPU instruction cycle takes 12 oscillator cycles.
Program Memory Lock Bits
The AT89S4D12 has two lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the following table. The self-timed
lock bit programming operation typically takes 40 ms.
Once programmed, the lock bits can only be unpro-
grammed with the Chip Erase operation.
Lock Bit Protection Modes(1)(2)
Program Lock Bits
LB1 LB2 Protection Type
1
U
U No internal memory lock feature.
2
P
U Programming of the Flash memory is disabled.
3
Notes:
P
P Same as mode 2, but verify is also disabled.
1. U = Unprogrammed
2. P = Programmed
Flash Programming Specification
Both the 128K bytes Data and 4K bytes Code flash mem-
ory arrays can be programmed using the serial SPI bus
while the RESET and TEST1 pins are pulled to VCC = 3.3V
(±10%). Both memory arrays are organized in 128-byte
sectors for programming and are written sector-by-sector,
similar to the Atmel AT29LV010A.
The serial interface consists of pins SCK (serial shift clock),
SDI (serial input) and SDO (serial output). After RESET
and TEST1 are set high, the Programming Enable instruc-
tion needs to be executed once before programming oper-
ations can occur. During device programming, pin TEST2
should be connected to Ground.
An auto-erase cycle is built into the self-timed Page Write
operation and there is no need to first execute the Chip
Erase instruction. The Chip Erase operation is self-timed
and typically takes 5 ms. Chip Erase turns the content of
every flash memory location in both the Code and Data
arrays into FFH.
The Code and Data memory arrays have separate address
spaces: 0000H to 0FFFH for Code memory and 00000H to
2FFFFH for Data memory.
The maximum serial clock (SCK) frequency used during
flash programming should be less than 500 KHz. The High
time of SCK should be 1.5 µs minimum and Low time
should be 0.5 µs minimum.
DATA Polling
The AT89S4D12 features DATA Polling to indicate the end
of a page write cycle. During a write cycle, an attempted
serial read of the last byte written will result in the comple-
ment of the written datum at bit D7. Once the write cycle
has been completed, true data are valid on all output data
bits, and the next write cycle may begin. DATA Polling may
begin any time after a write instruction has been executed.
Toggle Bit
The Toggle Bit provides another method to detect comple-
tion of a programming cycle. During a page write or chip
erase operation, successive attempts to read data from the
memory will result in output bit D6 toggling between ‘1’ and
‘0’. Once the program cycle has completed, output data bit
D6 will stop toggling and valid data will be presented.
Examining the toggle bit may begin any time during a pro-
gram cycle.
Ready/Busy
A third method to monitor the progress of programming is
provided by the RDY/BSY output signal. Pin P1.4/DSR is
pulled Low during programming to indicate BUSY and is
pulled High again when programming is done to indicate
READY.
Page Write
The Code and Data memory arrays are programmed on a
sector basis. If a byte of data is to be changed, data for the
entire 128-byte sector must be serially loaded into the
device using the appropriate serial interface instruction.
The data in any byte that is not loaded during the program-
ming of its sector will be indeterminate. The AT89S4D12
automatically does a sector erase to turn the whole sector
into FFH prior to loading the data into the sector. An erase
command is not required. The self-timed Page Write cycle
typically takes 5 ms (tWC).
(continued)
4-289
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