AT89S51 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT89S51' PDF : 31 Pages View PDF
20. Serial Programming Instruction Set
Instruction
Byte 1
Instruction Format
Byte 2
Byte 3
Programming Enable
1010 1100
0101 0011
xxxx xxxx
Chip Erase
1010 1100
Read Program Memory
(Byte Mode)
Write Program Memory
(Byte Mode)
Write Lock Bits(1)
0010 0000
0100 0000
1010 1100
Read Lock Bits
0010 0100
Read Signature Bytes 0010 1000
100x xxxx
xxxx
xxxx
1110 00
xxxx xxxx
xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxx xxx0
Byte 4
xxxx xxxx
0110 1001
(Output on
MISO)
xxxx xxxx
xxxx xxxx
xxx
xx
Operation
Enable Serial Programming
while RST is high
Chip Erase Flash memory
array
Read data from Program
memory in the byte mode
Write data to Program
memory in the byte mode
Write Lock bits. See Note (1).
Read back current status of
the lock bits (a programmed
lock bit reads back as a “1”)
Signature Byte Read Signature Byte
Read Program Memory
(Page Mode)
0011 0000
xxxx
Write Program Memory
(Page Mode)
0101 0000
xxxx
Note:
1. B1 = 0, B2 = 0 →Mode 1, no lock protection
B1 = 0, B2 = 1 →Mode 2, lock bit 1 activated
B1 = 1, B2 = 0 →Mode 3, lock bit 2 activated
B1 = 1, B2 = 1 →Mode 4, lock bit 3 activated
Byte 0
Byte 1...
Byte 255
Read data from Program
memory in the Page Mode
(256 bytes)
Byte 0
Byte 1...
Byte 255
Write data to Program
memory in the Page Mode
(256 bytes)
} Each of the lock bit modes need to be activated sequentially be-
fore Mode 4 can be executed.
After Reset signal is high, SCK should be low for at least 64 system clocks before it goes high to clock in the enable data
bytes. No pulsing of Reset signal is necessary. SCK should be no faster than 1/16 of the system clock at XTAL1.
For Page Read/Write, the data always starts from byte 0 to 255. After the command byte and upper address byte are
latched, each byte thereafter is treated as data until all 256 bytes are shifted in/out. Then the next instruction will be ready
to be decoded.
20 AT89S51
2487D–MICRO–6/08
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