AT90PWM2 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90PWM2' PDF : 365 Pages View PDF
AT90PWM2/3/2B/3B
Figure 15-1. 16-bit Timer/Counter Block Diagram(1)
Count
Clear
Direction
Control Logic
clkTn
Timer/Counter
TCNTn
TOP BOTTOM
=
=0
=
OCRnA
=
OCRnB
ICRn
TCCRnA
Fixed
TOP
Values
ICFn (Int.Req.)
Edge
Detector
TCCRnB
TOVn
(Int.Req.)
Clock Select
Edge
Detector
( From Prescaler )
OCnA
(Int.Req.)
Waveform
Generation
Tn
OCnA
OCnB
(Int.Req.)
Waveform
Generation
OCnB
Noise
Canceler
ICPSEL1
0
ICPnA
1
ICPnB
15.1.1 Registers
Note: 1. Refer toTable 3.1 on page 5 for Timer/Counter1 pin placement and description.
The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register
(ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit
registers. These procedures are described in the section “Accessing 16-bit Registers” on page
106. The Timer/Counter Control Registers (TCCRnx) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible
in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkTn).
The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter
value at all time. The result of the compare can be used by the Waveform Generator to generate
a PWM or variable frequency output on the Output Compare pin (OCnx). See “Output Compare
Units” on page 112. The compare match event will also set the Compare Match Flag (OCFnx)
which can be used to generate an Output Compare interrupt request.
4317K–AVR–03/2013
105
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