AT90PWM2 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90PWM2' PDF : 365 Pages View PDF
AT90PWM2/3/2B/3B
Figure 15-12. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
TOP - 1
TOP - 1
TOP
TOP
Old OCRnx Value
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
New OCRnx Value
Figure 15-13 shows the same timing data, but with the prescaler enabled.
Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICF n(if used
as TOP)
OCRnx
(Update at TOP)
TOP - 1
TOP - 1
TOP
TOP
Old OCRnx Value
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
New OCRnx Value
15.10 16-bit Timer/Counter Register Description
15.10.1
Timer/Counter1 Control Register A – TCCR1A
Bit
7
6
5
4
3
COM1A1 COM1A0 COM1B1 COM1B0
–
Read/Write
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
2
1
0
–
WGM11 WGM10 TCCR1A
R
R/W
R/W
0
0
0
• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A
• Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B
The COMnA1:0 and COMnB1:0 control the Output Compare pins (OCnA and OCnB respec-
tively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COMnB1:0 bit are written to one, the OCnB output overrides the normal port functionality of the
4317K–AVR–03/2013
124
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