AT90S2313-4PC View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90S2313-4PC' PDF : 92 Pages View PDF
1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must
be written to WDE even though it is set to 1 before the disable operation starts.
2. Within the next four clock cycles, write a logical “0” to WDE. This disables the
Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 14.
Table 14. Watchdog Timer Prescale Select(1)
WDP2
0
WDP1
0
WDP0
0
Number of
WDT Oscillator
Cycles
16K cycles
Typical Time-out
at VCC = 3.0V
47 ms
0
0
1
32K cycles
94 ms
0
1
0
64K cycles
0.19 s
0
1
1
128K cycles
0.38 s
1
0
0
256K cycles
0.75 s
1
0
1
512K cycles
1.5 s
1
1
0
1,024K cycles
3.0 s
1
1
1
2,048K cycles
6.0 s
Typical Time-out
at VCC = 5.0V
15 ms
30 ms
60 ms
0.12 s
0,24 s
0.49 s
0.97 s
1.9 s
Note:
1. The frequency of the Watchdog Oscillator is voltage-dependent, as shown in the
Electrical Characteristics section.
The WDR (Watchdog Reset) instruction should always be executed before the
Watchdog Timer is enabled. This ensures that the reset period will be in accordance
with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without
reset, the Watchdog Timer may not start counting from zero.
To avoid unintentional MCU Reset, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
38 AT90S2313
0839I–AVR–06/02
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