I/O Memory
0839I–AVR–06/02
AT90S2313
Figure 22. On-chip Data SRAM Access Cycles
T1
T2
T3
T4
System Clock Ø
Address
Data
WR
Data
RD
Prev. Address
Address
The I/O space definition of the AT90S2313 is shown in Table 1.
Table 1. AT90S2313 I/O Space(1)
Address Hex
$3F ($5F)
$3D ($5D)
$3B ($5B)
$3A ($5A)
$39 ($59)
$38 ($58)
$35 ($55)
$33 ($53)
$32 ($52)
$2F ($4F)
$2E ($4E)
$2D ($4D)
$2C ($4C)
$2B ($4B)
$2A ($4A)
$25 ($45)
$24 ($44)
$21 ($41)
$1E ($3E)
$1D ($3D)
$1C ($3C)
$18 ($38)
$17 ($37)
$16 ($36)
Name
SREG
SPL
GIMSK
GIFR
TIMSK
TIFR
MCUCR
TCCR0
TCNT0
TCCR1A
TCCR1B
TCNT1H
TCNT1L
OCR1AH
OCR1AL
ICR1H
ICR1L
WDTCR
EEAR
EEDR
EECR
PORTB
DDRB
PINB
Function
Status Register
Stack Pointer Low
General Interrupt MaSK Register
General Interrupt Flag Register
Timer/Counter Interrupt MaSK Register
Timer/Counter Interrupt Flag Register
MCU general Control Register
Timer/Counter 0 Control Register
Timer/Counter 0 (8-bit)
Timer/Counter 1 Control Register A
Timer/Counter 1 Control Register B
Timer/Counter 1 High Byte
Timer/Counter 1 Low Byte
Output Compare Register 1 High Byte
Output Compare Register 1 Low Byte
T/C 1 Input Capture Register High Byte
T/C 1 Input Capture Register Low Byte
Watchdog Timer Control Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register
Data Register, Port B
Data Direction Register, Port B
Input Pins, Port B
15