AT90S2313-4PI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90S2313-4PI' PDF : 92 Pages View PDF
AT90S2313
The TEMP Register is also used when accessing TCNT1 and OCR1A. If the main pro-
gram and interrupt routines perform access to registers using TEMP, interrupts must be
disabled during access from the main program or interrupts if interrupts are re-enabled.
Timer/Counter1 in PWM Mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register1
(OCR1A) form an 8-, 9-, or 10-bit, free-running, glitch-free and phase-correct PWM with
output on the PB3(OC1) pin. Timer/Counter1 acts as an up/down counter, counting up
from $0000 to TOP (see Table 11), where it turns and counts down again to zero before
the cycle is repeated. When the counter value matches the contents of the 8, 9 or 10
least significant bits of OCR1A, the PB3(OC1) pin is set or cleared according to the set-
tings of the COM1A1 and COM1A0 bits in the Timer/Counter1 Control Register
(TCCR1). Refer to Table 12 for details.
Table 11. Timer TOP Values and PWM Frequency
PWM Resolution
Timer TOP Value
8-bit
$00FF (255)
9-bit
$01FF (511)
10-bit
$03FF(1023)
Frequency
fTC1/510
fTC1/1022
fTC1/2046
Table 12. Compare1 Mode Select in PWM Mode(1)
COM1A1
0
0
1
1
COM1A0
0
1
0
1
Effect on OC1
Not connected
Not connected
Cleared on compare match, upcounting. Set on compare match,
down-counting (non-inverted PWM).
Cleared on compare match, downcounting. Set on compare match,
up-counting (inverted PWM).
Note: 1. The initial state of the OC1 output line is undefined.
Note that in the PWM mode, the 10 least significant OCR1A bits, when written, are
transferred to a temporary location. They are latched when Timer/Counter1 reaches
TOP. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of
an unsynchronized OCR1A write. See Figure 32 for an example.
Figure 32. Effects on Unsynchronized OCR1 Latching
Compare Value changes
Compare Value changes
35
0839I–AVR–06/02
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