AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
AIC: Advanced Interrupt Controller
The AT91M40400 has an 8-level priority, individually
maskable, vectored interrupt controller. This feature sub-
stantially reduces the software and real time overhead in
handling internal and external interrupts.
The interrupt controller is connected to the NFIQ (fast inter-
rupt request) and the NIRQ (standard interrupt request)
inputs of the ARM7TDMI processor. The processor’s NFIQ
line can only be asserted by the external fast interrupt
request input: FIQ. The NIRQ line can be asserted by the
Figure 32. Interrupt Controller Block Diagram
interrupts generated by the on-chip peripherals and the
external interrupt request lines: IRQ0 to IRQ2.
The 8-level priority encoder allows the customer to define
the priority between the different NIRQ interrupt sources.
Internal sources are programmed to be level sensitive or
edge triggered. External sources can be programmed to be
positive or negative edge triggered or high or low level sen-
sitive.
The interrupt sources are listed in Table 5 and the AIC pro-
grammable registers in Table 6.
FIQ Source
Memorization
NFIQ
Manager
NFIQ
Advanced Peripheral
Bus (APB)
Control
Logic
ARM7TDMI
Core
Internal Interrupt Sources
External Interrupt Sources
Memorization
Priority
Controller
NIRQ
Manager
NIRQ
Note: After a hardware reset, the AIC pins are controlled by the PIO Controller. They must be configured to be controlled
by the peripheral before being used.
34
AT91M40400
Share Link: 
