AT91M40400 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91M40400' PDF : 116 Pages View PDF
AT91M40400
TC User Interface
TC Base Address:
0xFFFE0000
Table 10. TC Global Memory Map
Offset
Channel/Register
0x00
TC Channel 0
0x40
TC Channel 1
0x80
TC Channel 2
0xC0
TC Block Control Register
0xC4
TC Block Mode Register
Name
TC_BCR
TC_BMR
Access
See Table 11
See Table 11
See Table 11
Write only
Read/Write
Reset State
---
0
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the TC block. TC Channels are controlled
by the registers listed in Table 11. The offset of each of the Channel registers in Table 11 is in relation to the offset of the
corresponding channel as mentioned in Table 10.
Table 11. TC Channel Memory Map
Offset
Register
Name
Access
Reset State
0x00
Channel Control Register
TC_CCR
Write only
---
0x04
Channel Mode Register
TC_CMR
Read/Write
0
0x08
Reserved
---
0x0C
Reserved
---
0x10
0x14
0x18
Counter Value
Register A
Register B
TC_CV
Read/Write
0
TC_RA
Read/Write(1)
0
TC_RB
Read/Write(1)
0
0x1C
Register C
TC_RC
Read/Write
0
0x20
Status Register
TC_SR
Read only
---
0x24
Interrupt Enable Register
TC_IER
Write only
---
0x28
Interrupt Disable Register
TC_IDR
Write only
---
0x2C
Interrupt Mask Register
TC_IMR
Read only
0
Note: 1. Read only if WAVE = 0
91
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