AT91SAM View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'AT91SAM' PDF : 1185 Pages View PDF
8.4 Peripheral Signals Multiplexing on I/O Lines
The SAM9G45 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplexes the I/O lines of
the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B.
The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multi-
plexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for
the user’s own comments; they may be used to track how pins are defined in an application.
Note that some peripheral function which are output only, might be duplicated within the both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is men-
tioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as
soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Periph-
eral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corre-
sponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines,
which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in
this case.
To amend EMC, programmable delay has been inserted on PIO lines able to run at high speed.
SAM9G45 [DATASHEET] 25
6438K–ATARM–12-Feb-13
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