AT91SAM7SE32 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM7SE32' PDF : 47 Pages View PDF
– Two for each USART
– Two for the Debug Unit
– Two for the Serial Synchronous Controller
– Two for the Serial Peripheral Interface
– One for the Analog-to-digital Converter
• Low bus arbitration overhead
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
• Next Pointer management for reducing interrupt latency requirements
20 AT91SAM7SE512/256/32 [Advance Information Summary]
6222AS–ATARM–21-Aug-06
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