AT91SAM9260B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9260B-CU' PDF : 47 Pages View PDF
AT91SAM9260
6.4 PIO Controllers
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor.
Refer to the section on DC Characteristics in “AT91SAM9260 Electrical Characteristics” for
more information. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
6.5 I/O Line Drive Levels
The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA per-
manently except PC4 to PC31 that are VDDIOM powered.
6.6 Shutdown Logic Pins
The SHDN pin is a tri-state output pin, which is driven by the Shutdown Controller. There is no
internal pull-up. An external pull-up tied to VDDBU is needed and its value must be higher than
1 MΩ. The resistor value is calculated according to the regulator enable implementation and the
SHDN level.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
6.7 Slow Clock Selection
The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the
on-chip RC oscillator.
Table 6-1 defines the states for OSCSEL signal.
Table 6-1.
OSCSEL
0
1
Slow Clock Selection
Slow Clock
Internal RC
External 32768 Hz
Startup Time
240 µs
1200 ms
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The
32,768 Hz startup delay is 1200 ms whereas it is 240 µs for the internal RC oscillator (refer to
Table 6-1). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the
device.
7. Processor and Architecture
7.1 ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
15
6221JS–ATARM–17-Jul-09
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