AT91SAM9263B-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9263B-CU' PDF : 52 Pages View PDF
10.2.1 Peripheral Interrupts and Clock Control
10.2.1.1 System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
z the SDRAM Controller
z the Debug Unit
z the Periodic Interval Timer
z the Real-Time Timer
z the Watchdog Timer
z the Reset Controller
z the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt
Controller.
10.2.1.2 External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated
Peripheral ID. However, there is no clock control associated with these peripheral IDs.
10.2.1.3 Timer Counter Interrupts
The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the
Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching
the right Interrupt Service Routine.
The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 19
disables the clock of the 3 channels.
10.3
Peripherals Signals Multiplexing on I/O Lines
The AT91SAM9263 device features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines
of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The
multiplexing tables define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two
columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to
track how pins are defined in an application.
Note that some peripheral functions which are output only may be duplicated within both tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is specified, the
PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is
released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets
low.
If a signal name is specified in the “Reset State” column, the PIO Line is assigned to this function and the corresponding
bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require
the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.
SAM9263 [Summary] 32
6249IS–ATARM–28-Jan-13
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