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AT91SAM9G10-CU View Datasheet(PDF) - Atmel Corporation

Part Name
Description
MFG CO.
AT91SAM9G10-CU
Atmel
Atmel Corporation Atmel
'AT91SAM9G10-CU' PDF : 730 Pages View PDF
Table 11-1. ARM9TDMIModes and Registers Layout
User and
System Mode
R11
R12
R13
R14
PC
Supervisor
Mode
R11
R12
R13_SVC
R14_SVC
PC
Abort Mode
R11
R12
R13_ABORT
R14_ABORT
PC
Undefined
Mode
R11
R12
R13_UNDEF
R14_UNDEF
PC
Interrupt
Mode
R11
R12
R13_IRQ
R14_IRQ
PC
Fast
Interrupt
Mode
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
PC
CPSR
CPSR
SPSR_SVC
CPSR
SPSR_ABORT
CPSR
SPSR_UNDEF
CPSR
SPSR_IRQ
CPSR
SPSR_FIQ
Mode-specific banked
registers
The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional
register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose
registers used to hold either data or address values. Register r14 is used as a Link register that
holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a pro-
gram counter (PC), whereas the Current Program Status Register (CPSR) contains condition
code flags and the current mode bits.
In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers
(r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding
banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val-
ues (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when
BL or BLX instructions are executed within interrupt or exception routines. There is another reg-
ister called Saved Program Status Register (SPSR) that becomes available in privileged modes
instead of CPSR. This register contains condition code flags and the current mode bits saved as
a result of the exception that caused entry to the current (privileged) mode.
In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey ARM Procedure Call
Standard (APCS) which defines:
• constraints on the use of registers
• stack conventions
• argument passing and result return
The Thumb state register set is a subset of the ARM state set. The programmer has direct
access to:
• Eight general-purpose registers r0-r7
• Stack pointer, SP
• Link register, LR (ARM r14)
• PC
40 AT91SAM9G10
6462A–ATARM–03-Jun-09
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