AT91SAM9G10-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9G10-CU' PDF : 730 Pages View PDF
AT91SAM9G10
12.3.2
Test Environment
Figure 12-3 on page 55 shows a test environment example. Test vectors are sent and inter-
preted by the tester. In this example, the “board in test” is designed using a number of JTAG-
compliant devices. These devices can be connected to form a single scan chain.
Figure 12-3. Application Test Environment Example
Test Adaptor
Tester
JTAG
Interface
ICE/JTAG
Connector
Chip n
Chip 2
AT91SAM9G10
Chip 1
AT91SAM9G10-based Application Board In Test
12.4 Debug and Test Pin Description
Table 12-1.
Pin Name
NRST
TST
TCK
TDI
TDO
TMS
NTRST
RTCK
JTAGSEL
DRXD
DTXD
Debug and Test Pin List
Function
Reset/Test
Microcontroller Reset
Test Mode Select
ICE and JTAG
Test Clock
Test Data In
Test Data Out
Test Mode Select
Test Reset Signal
Returned Test Clock
JTAG Selection
Debug Unit
Debug Receive Data
Debug Transmit Data
Type
Active Level
Input/Output
Input
Low
High
Input
Input
Output
Input
Input
Low
Output
Input
Input
Output
55
6462A–ATARM–03-Jun-09
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