AT91SAM9G20B-CFU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9G20B-CFU' PDF : 42 Pages View PDF
AT91SAM9G20 Summary
10.4.9
Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
• Support physical layer management through MDIO interface
10.4.10
Image Sensor Interface
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• Preview Path up to 640 x 480 in RGMB mode, 2048 x2048 in grayscale mode
• Support for packed data formatting for YCbCr 4:2:2 formats
• Preview scaler to generate smaller size image
• Programmable frame capture rate
10.4.11
Analog-to-Digital Converter
• 4-channel ADC
• 10-bit 312K samples/sec. Successive Approximation Register ADC
• -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity
• Individual enable and disable of each channel
• External voltage reference for better accuracy on low voltage inputs
• Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter
0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep
mode after conversions of all enabled channels
• Four analog inputs shared with digital signals
37
6384CS–ATARM–11-Mar-09
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