AT91SAM9G45-CU View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT91SAM9G45-CU' PDF : 55 Pages View PDF
10.4.2 Test Environment
Figure 10-3 on page 54 shows a test environment example. Test vectors are sent and interpreted by the tester. In
this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be
connected to form a single scan chain.
Figure 10-3. Application Test Environment Example
JTAG
Interface
Test Adaptor
Tester
ICE/JTAG Chip n
Chip 2
SAM9G45
Chip 1
SAM9G45-based Application Board In Test
10.5 Debug and Test Pin Description
Table 10-1.
Pin Name
NRST
TST
NTRST
TCK
TDI
TDO
TMS
RTCK
JTAGSEL
DRXD
DTXD
Debug and Test Pin List
Function
Reset/Test
Microcontroller Reset
Test Mode Select
ICE and JTAG
Test Reset Signal
Test Clock
Test Data In
Test Data Out
Test Mode Select
Returned Test Clock
JTAG Selection
Debug Unit
Debug Receive Data
Debug Transmit Data
Type
Active Level
Input/Output
Input
Low
High
Input
Low
Input
Input
Output
Input
Output
Input
Input
Output
SAM9G45 [DATASHEET] 54
6438K–ATARM–12-Feb-13
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