ATEMGA128-16AI View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128-16AI' PDF : 395 Pages View PDF
Timer/Counter Timing
Diagrams
As Figure 54 shows the output generated is, in contrast to the phase correct mode, sym-
metrical in all periods. Since the OCRnx Registers are updated at BOTTOM, the length
of the rising and the falling slopes will always be equal. This gives symmetrical output
pulses and is therefore frequency correct.
Using the ICRn Register for defining TOP works well when using fixed TOP values. By
using ICRn, the OCRnA Register is free to be used for generating a PWM output on
OCnA. However, if the base PWM frequency is actively changed by changing the TOP
value, using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of
PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-
inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0
to 3 (See Table 60 on page 134). The actual OCnx value will only be visible on the port
pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM
waveform is generated by setting (or clearing) the OCnx Register at the compare match
between OCRnx and TCNTn when the counter increments, and clearing (or setting) the
OCnx Register at compare match between OCRnx and TCNTn when the counter
decrements. The PWM frequency for the output when using phase and frequency
correct PWM can be calculated by the following equation:
fOCnxPFCPWM
=
------f--c---l-k--_---I-/-O--------
2 ⋅ N ⋅ TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
set to high for non-inverted PWM mode. For inverted PWM the output will have the
opposite logic values.
If OCRnA is used to define the TOP value (WGMn3:0 = 9) and COMnA1:0 = 1, the
OCnA Output will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore
shown as a clock enable signal in the following figures. The figures include information
on when interrupt flags are set, and when the OCRnx Register is updated with the
OCRnx buffer value (only for modes utilizing double buffering). Figure 55 shows a timing
diagram for the setting of OCFnx.
130 ATmega128
2467O–AVR–10/06
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