ATEMGA128-16AI View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATEMGA128-16AI' PDF : 395 Pages View PDF
ATmega128
corresponding interrupt vector (see “Interrupts” on page 59) is executed when the
OCF3A flag, located in ETIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare B Match Interrupt is enabled. The
corresponding interrupt vector (see “Interrupts” on page 59) is executed when the
OCF3B flag, located in ETIFR, is set.
• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Overflow Interrupt is enabled. The corresponding
interrupt vector (see “Interrupts” on page 59) is executed when the TOV3 flag, located in
ETIFR, is set.
• Bit 1 – OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter3 Output Compare C Match Interrupt is enabled. The
corresponding interrupt vector (see “Interrupts” on page 59) is executed when the
OCF3C flag, located in ETIFR, is set.
• Bit 0 – OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts glo-
bally enabled), the Timer/Counter1 Output Compare C Match Interrupt is enabled. The
corresponding interrupt vector (see “Interrupts” on page 59) is executed when the
OCF1C flag, located in ETIFR, is set.
Timer/Counter Interrupt Flag
Register – TIFR
Bit
Read/Write
Initial Value
7
OCF2
R/W
0
6
TOV2
R/W
0
5
ICF1
R/W
0
4
OCF1A
R/W
0
3
OCF1B
R/W
0
2
TOV1
R/W
0
1
OCF0
R/W
0
0
TOV0
R/W
0
TIFR
Note:
This register contains flag bits for several Timer/Counters, but only timer 1 bits are
described in this section. The remaining bits are described in their respective timer
sections.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture
Register (ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 flag is set
when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt vector is executed. Alter-
natively, ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register A (OCR1A).
Note that a forced output compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A interrupt vector is
executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 3 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Out-
put Compare Register B (OCR1B).
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