ATEMGA128 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'ATEMGA128' PDF : 395 Pages View PDF
ATmega128
Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)
T1
T2
T3
T4
T5
System Clock (CLKCPU)
ALE
T6
T7
A15:8 Prev. addr.
Address
DA7:0 Prev. data
Address XX
Data
WR
DA7:0 (XMBK = 0) Prev. data
Address
Data
DA7:0 (XMBK = 1) Prev. data
Address
Data
RD
XMEM Register Description
MCU Control Register –
MCUCR
External Memory Control
Register A – XMCRA
Note:
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper
sector) or SRW00 (lower sector).
The ALE pulse in period T7 is only present if the next instruction accesses the RAM
(internal or external).
Bit
Read/Write
Initial Value
7
6
5
SRE SRW10
SE
R/W
R/W
R/W
0
0
0
4
SM1
R/W
0
3
SM0
R/W
0
2
SM2
R/W
0
1
IVSEL
R/W
0
0
IVCE
R/W
0
MCUCR
• Bit 7 – SRE: External SRAM/XMEM Enable
Writing SRE to one enables the External Memory Interface.The pin functions AD7:0,
A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit over-
rides any pin direction settings in the respective data direction registers. Writing SRE to
zero, disables the External Memory Interface and the normal pin and data direction set-
tings are used.
• Bit 6 – SRW10: Wait-state Select Bit
For a detailed description in non-ATmega103 compatibility mode, see common descrip-
tion for the SRWn bits below (XMCRA description). In ATmega103 compatibility mode,
writing SRW10 to one enables the wait-state and one extra cycle is added during
read/write strobe as shown in Figure 14.
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
–
SRL2
SRL1
SRL0 SRW01 SRW00 SRW11
–
XMCRA
R
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
• Bit 7 – Res: Reserved Bit
This is a reserved bit and will always read as zero. When writing to this address location,
write this bit to zero for compatibility with future devices.
• Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit
31
2467O–AVR–10/06
Share Link: 
